PLL and Jitter Spectrum Analysis using the 86100C Digital Communications Analyzer
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Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods
Charge-Pump Phase-locked loops are currently used in a variety of signal generation applications. Due to the usefulness of the device CP-PLLs are now commonplace inclusions in SOC designs, and ultimately determine performance of other SOC blocks, such as ADC’s, DAC’s, RF functions and fibre communications channels. In many situations, only simple frequency lock tests are carried out on the PLL ...
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